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| Features * * * * * * * * * Supply Voltage Range 3V to 4.6V (Unregulated) Auxiliary Voltage Regulator On-chip Low Current Consumption Few Low Cost External Components No Mechanical Tuning Required Non-blindslot and Blindslot Operation Unlimited Multislot Operation with Advanced Closed-loop Modulation Supports Multiple Reference Clocks (10.368 MHz/13.824 MHz/20.736 MHz) TX Preamplifier with 0 dBm Output Power at 1.9 GHz and Ramp-signal Generator for SiGe Power Amplifier DECT Single-chip Transceiver T2801 1. Description The T2801 is an RF IC for low-power DECT applications. The QFN48 packaged IC is a complete transceiver including image rejection mixer, IF amplifier, FM demodulator, baseband filter, RSSI, TX preamplifier, power-ramping generator for power amplifiers, integrated synthesizer, fully integrated VCO, TX filter and modulation compensation circuit for advanced closed-loop modulation concept. No mechanical tuning is necessary in production. Figure 1-1. Block Diagram MIXER IF_IN OUT IR MIXER RF_IN DEMOD BB FILTER RAMP_OUT RAMP_SET RAMP GEN D/A RSSI DEMOD DAC RSSI GF TX_DATA DEMOD IF_TANK IF AMP 1 IF AMP 2 BB_OUT TANK CF VCO TX / RX SWITCH PC TX_OUT f :n TX DRIVER PD MCC 3-WIRE BUS CLOCK DATA ENABLE PU_VCO VCO REG AUX REG CP RC f :n CTRL LOGIC RX_ON TX_ON PU_RX/TX PU_PLL VREG_VCO VS_VCO VREG VS_REG VTUNE GND_VCO PU_REG REG_CTRL CP I_CPSW LD REF_CLK Rev. 4567B-DECT-03/06 Table 1-1. Name AUX REG BBF CP DAC DEMOD GF IF AMP1 IF AMP2 IR MIXER MCC PC PD RAMP GEN RC RSSI TX DRIVER Functional Block Description Description Auxiliary voltage regulator Baseband filter Charge pump D/A converter for demodulator tuning Demodulator Gaussian filter for transmit data 1st intermediate frequency amplifier 2nd intermediate frequency amplifier Image rejection mixer Modulation compensation circuit Programmable counter Phase detector Ramp-signal generator Reference counter Received signal-strength indicator Buffer amplifier for TX_OUT Switches VCO signal to IR mixer resp. TX driver Voltage-controlled oscillator Voltage regulator for VCO TX/RX SWITCH VCO VCO REG 2 T2801 4567B-DECT-03/06 T2801 2. Pin Configuration Figure 2-1. Pinning QFN48 MIXER_OUT2 MIXER_OUT1 RAMP_SET PU_RX/TX PU_PULL GND_PLL VS_MIXER TX_DATA PU_VCO I_CPSW 48 CLOCK DATA ENABLE REF_CLK LD PU_REG VS_PLL VREG REG_CTRL VS_REG GND_CP VS_CP 1 2 3 4 5 6 7 8 9 10 11 12 47 46 45 44 43 42 41 40 39 TX_ON 38 RX_ON 37 36 35 34 33 32 31 RAMP_OUT IF_IN2 IF_IN1 VS_IF TX_OUT GND3 RF_IN2 RF_IN1 GND2 IF_TANK2 IF_TANK1 RSSI T2801 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 GND1 CP VREG_VCO GND_VCO REG_DEC DAC_DEC VS_VCO DEMOD_TANK2 DEMOD_TANK1 BB_OUT VTUNE BB_CF 3 4567B-DECT-03/06 Table 2-1. Pin Pin Description Symbol Function VS_PLL 7 Configuration 1 2 3 CLOCK DATA ENABLE 3-wire-bus: Clock input 3-wire-bus: Data input 3-wire-bus: Enable input CLOCK DATA ENABLE 1,2,3 5k 5k GND_PLL 43 VS_PLL 7 4 REF_CLK Reference-frequency input REF_CLK 4 10k 10k GND_PLL 43 LD 5 100 5 LD Lock-detect output GND_PLL 43 PU_REG 6 6 PU_REG Power-up input for auxiliary voltage regulator GND_PLL 43 25k 25k 4 T2801 4567B-DECT-03/06 T2801 Table 2-1. Pin Pin Description (Continued) Symbol Function VS_PLL 7 VS_REG 10 VS_CP 12 VS_VCO 14 Configuration GND1 18 GND2 28 GND3 31 GND_VCO 16 GND_CP 11 7 VS_PLL PLL supply voltage VS_IF 33 VS_MIXER 42 GND_PLL 43 VS_REG 10 VS_PLL 7 REG_CTRL 9 VREG 8 8 9 10 VREG REG_CTRL VS_REG Auxiliary voltage-regulator output Auxiliary voltage-regulator control output Auxiliary voltage-regulator supply voltage GND_PLL 43 VS_CP 12 VS_PLL 7 11 12 13 GND_CP VS_CP CP Charge-pump ground Charge-pump supply voltage Charge-pump output CP 13 GND_PLL 43 GND_CP 11 5 4567B-DECT-03/06 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS_VCO 14 VS_PLL 7 14 15 16 VS_VCO VREG_VCO GND_VCO VCO voltage-regulator supply voltage VCO voltage-regulator control output VCO ground VREG_VCO 15 GND_PLL 43 GND_VCO 16 VREG_VCO 15 VS_PLL 7 17 VTUNE VCO tuning voltage input VTUNE 17 GND_PLL 43 GND_VCO 16 VS_PLL 7 VS_REG 10 VS_CP 12 VS_VCO 14 GND1 18 GND2 28 GND3 31 GND_VCO 16 GND_CP 11 18 GND1 Ground VS_IF 33 VS_MIXER 42 GND_PLL 43 6 T2801 4567B-DECT-03/06 T2801 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS_MIXER 42 10k 10k VS_IF 33 DEMOD TANK2 20 19 20 DEMOD_TANK1 DEMOD_TANK2 Demodulator tank circuit Demodulator tank circuit DEMOD TANK1 19 GND2 28 GND1 18 VREG_VCO 15 VS_PLL 7 DAC_DEC 21 10k 21 DAC_DEC Decoupling pin for VCO_DAC GND_PLL 43 GND_VCO 16 400 VREG_VCO 15 VS_IF 33 2k 22 REG_DEC Decoupling pin for VCO_REG REG_DEC 22 GND2 28 GND_VCO 16 42k 7 4567B-DECT-03/06 Table 2-1. Pin Pin Description (Continued) Symbol Function VS_IF 33 Configuration 23 BB_CF Baseband filter corner-frequency control input BB_CF 23 GND2 28 GND1 18 VS_IF 33 24 BB_OUT Baseband filter output BB_OUT 24 GND2 28 GND1 18 VS_IF 33 25 RSSI Received signal-strength indicator output RSSI 25 13k GND2 28 VS_IF 33 26 27 IF_TANK1 IF_TANK2 IF tank circuit IF tank circuit 13k RSSI 25 GND2 28 8 T2801 4567B-DECT-03/06 T2801 Table 2-1. Pin Pin Description (Continued) Symbol Function VS_PLL 7 VS_REG 10 VS_CP 12 VS_VCO 14 Configuration GND1 18 GND2 28 GND3 31 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 28 GND2 Ground VS_IF 33 VS_MIXER 42 29 30 RF_IN1 RF_IN2 RF input of image reject mixer RF input of image reject mixer RF_IN1 29 RF_IN2 30 GND2 28 VS_PLL 7 VS_REG 10 VS_CP 12 VS_VCO 14 GND1 18 GND2 28 GND3 31 GND_VCO 16 GND_CP 11 31 GND3 Ground VS_IF 33 VS_MIXER 42 GND_PLL 43 9 4567B-DECT-03/06 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration TX_OUT 32 32 TX_OUT TX driver amplifier output for PA GND3 31 VS_PLL 7 VS_REG 10 VS_CP 12 VS_VCO 14 GND1 18 GND2 28 GND3 31 GND_VCO 16 GND_CP 11 33 VS_IF IF amplifier supply voltage VS_IF 33 VS_MIXER 42 GND_PLL 43 VS_IF 33 34 35 IF_IN1 IF_IN2 IF input of IF amplifier IF input of IF amplifier IF_IN1 34 4.3k IF_IN2 35 GND2 28 VS_MIXER 42 VS_IF 33 36 RAMP_OUT Ramp-generator output for PA power ramping RAMP_OUT 36 GND2 28 10 T2801 4567B-DECT-03/06 T2801 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS_MIXER 42 VS_IF 33 37 RAMP_SET Slew-rate setting of ramping signal 1k 100 RAMP SET 37 GND2 25 VS_IF 33 38 39 RX_ON TX_ON RX control input TX control input RX_ON TX_ON 38, 39 5k 5k GND2 28 GND1 18 VS_IF 33 MIXER_ OUT1 40 270 270 VS_MIXER 42 MIXER_ OUT2 41 40 41 MIXER_OUT1 MIXER_OUT2 Mixer output to SAW filter Mixer output to SAW filter GND2 28 11 4567B-DECT-03/06 Table 2-1. Pin Pin Description (Continued) Symbol Function VS_PLL 7 VS_REG 10 VS_CP 12 VS_VCO 14 Configuration GND1 18 GND2 28 GND3 31 GND_VCO 16 GND_CP 11 42 43 VS_MIXER GND_PLL Mixer supply voltage PLL ground VS_IF 33 VS_MIXER 42 GND_PLL 43 VS_VCO 14 44 PU_VCO VCO power-up input PU_VCO 44 GND_PLL 7 GND_VCO 16 5k 5k PU_RX/TX 45 25k 25k 45 PU_RX/TX RX/TX power-up input GND_PLL 7 GND1 18 12 T2801 4567B-DECT-03/06 T2801 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration PU_RX/TX 45 25k 25k 46 PU_PLL PLL power-up input GND_PLL 7 GND1 18 VS_PLL 7 47 TX_DATA TX data input of Gaussian filter and modulation-compensation circuit TX_DATA 47 5k 5k GND_PLL 43 VS_PLL 7 48 I_CPSW Charge pump switch input controls charge pump current I_CPSW 48 5k GND_PLL 43 13 4567B-DECT-03/06 3. Functional Description 3.1 Receiver The RF signal at RF_IN is fed to an image rejection mixer IR_MIXER with its differential outputs MIXER_OUT1 and MIXER_OUT2 driving an IF-SAW filter at 110.592 MHz or 112.32 MHz. The IF amplifiers IF_AMP1 and IF_AMP2 with an external IF_TANK and an integrated RSSI function feed the signal to the demodulator DEMOD working at f = fIF/2 ([55 MHz) and finally to an integrated baseband filter BB. For demodulator tuning in production, an integrated 5-bit Digital-to-Analog (D/A) converter is provided to control the on-chip varicap diode. 3.2 Transmitter The transmit data at TX_DATA is filtered by an integrated Gaussian Filter (GF) and fed to the fully integrated VCO operating at twice the output frequency. After modulation, the signal is frequency-divided by 2 and fed via a TX/RX SWITCH to the TX_DRIVER. This bus-controlled driver amplifier supplies typical +3 dBm output power at TX_OUT. An integrated ramp-signal generator, RAMP_GEN, provides a ramp signal at RAMP_OUT for the external power amplifier. The slope of the ramp signal is controlled by a capacitor at the RAMP_SET pin. 3.3 Synthesizer The IR_MIXER, the TX_DRIVER and the programmable counter PC are driven by the fully integrated VCO (including on-chip inductors and varactors). An 3-bit digital-to-analog converter is used to pretune the frequency. The output signal is frequency-divided to supply the desired frequency to the TX_DRIVER, 0/90 degree phase shifter for the IR_MIXER and to be used by the PC for the phase detector PD (fPD = 3.456 MHz). Unlimited multislot operation is possible by using the integrated advanced closed-loop modulation concept based on the modulation compensation circuit MCC. 3.4 Power Supply An integrated bandgap-stabilized voltage regulator for use with an external low-cost PNP transistor is implemented. Multiple power-down and current saving modes are provided. 14 T2801 4567B-DECT-03/06 T2801 Figure 3-1. PLL Principle RF_IN Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = fPD x (SMC x 32 + SSC) fVCO ext. loop filter Phase frequency detector PD fPD = 3.456 MHz PA driver Charge pump VCO Divider by 2 Mixer VCO DAC GF_DATA Controlled phase shifting Modulation compensation MCC Gaussian filter GF Reference counter RC REF_CLK 10.368MHz 13.824MHz 20.736MHz SMC 3 4 6 6.912 MHz 1.152 Mbit/s PLL reference Frequency REF_CLK Baseband controller TX_DATA 15 4567B-DECT-03/06 Table 3-1 shows the LO frequencies for RX and TX for the DECT band plus additional channels for the extended DECT band. Intermediate frequencies of 110.592 MHz and 112.32 MHz are supported. Table 3-1. Mode TX TX TX TX TX TX TX TX TX TX RX RX RX RX RX RX RX RX RX RX RX RX RX RX RX RX RX RX RX RX 110.592 110.592 110.592 110.592 110.592 110.592 110.592 110.592 110.592 110.592 112.320 112.320 112.320 112.320 112.320 112.320 112.320 112.320 112.320 112.320 LO Frequencies fIF/MHz Channel C9 C8 ... C1 C0 C10 C11 ... C29 C30 C9 C8 ... C1 C0 C10 C11 ... C29 C30 C9 C8 ... C1 C0 C10 C11 ... C29 C30 fANT/MHz 1881.792 1883.520 ... 1895.616 1897.344 1899.072 1900.800 ... 1931.904 1933.632 1881.792 1883.520 ... 1895.616 1897.344 1899.072 1900.800 ... 1931.904 1933.632 1881.792 1883.520 ... 1895.616 1897.344 1899.072 1900.800 ... 1931.904 1933.632 fVCO/MHz 1881.792 1883.520 ... 1895.616 1897.344 1899.072 1900.800 ... 1931.904 1933.632 1771.200 1772.928 ... 1785.024 1786.752 1788.480 1790.208 ... 1821.312 1823.040 1769.472 1771.200 ... 1783.296 1785.024 1786.752 1788.480 ... 1819.584 1821.312 SMC 34 34 ... 34 34 34 34 ... 34 34 32 32 ... 32 32 32 32 ... 32 32 32 32 ... 32 32 32 32 ... 32 32 SSC 1 2 ... 9 10 11 12 ... 30 31 1 2 ... 9 10 11 12 ... 30 31 0 1 ... 8 9 10 11 ... 29 30 Formula: TX: fANT = fVCO = 1.728 MHz x (32 x SMC + SSC) RX: fANT = 1.728 MHz x (32 x SMC + SSC) + fIF 16 T2801 4567B-DECT-03/06 T2801 4. Control Signals Table 4-1. Signal I_CPSW PU_REG PU_VCO PU_RX/TX PU_PLL RX_ON TX_ON Data Word 1, Bit D10 Data Word 1, Bit D9 Control Signals - Functions Function Controls the charge pump current Activates AUX voltage regulator supplying the complete transceiver Activates VCO voltage regulator which supplies only the VCO Activates RX/TX blocks Activates PLL circuits: PC, PD, CP, RC Activates RX circuits: BBF, DEMOD, IF AMP, IR MIXER Activates TX circuits: TX-DRIVER, RAMP GEN. Starts RAMP SIGNAL at RAMP OUT Activates GF in TX mode Activates MCC in TX mode Table 4-2. Mode PU_REG PU_VCO PU_RX/TX PU_PLL RX_ON TX_ON BB filter Demodulator Control Signals - Modes TX Mode 1 1 1 1 0 1 OFF OFF OFF OFF OFF ON ON ON ON ON ON ON ON ON 54 RX Mode 1 1 1 1 1 0 ON ON ON ON ON OFF OFF OFF ON ON OFF ON OFF ON 85 RSSI Only 1 1 1 1 1 1 OFF OFF ON ON ON OFF OFF OFF ON ON OFF ON OFF ON 80 IF amplifiers and RSSI IR mixer RX switch TX switch TX driver Ramp generator Programmable counter Voltage-controlled oscillator Gaussian filter Phase detector/charge pump Modulation compensation circuit Reference counter Typical current consumption/mA at VS = 3.2 V 17 4567B-DECT-03/06 5. Serial Programming Bus The transceiver is programmed by the 3-wire bus (CLOCK, DATA and ENABLE). After setting enable signal to low condition, on the rising edge of the clock signal, the data is transferred bit by bit into the shift register, starting with the MSB-bit. After enable returning to high condition, the programmed information is loaded into the addressed latches, according to the addressbit condition (last bit). Additional leading bits are ignored and there is no check made on how many pulses arrived during enable-low condition. During enable low condition, the bus current is increased to speed up the bus logic. The programming of the transceiver is separated into two data words. Data word 1 controls mainly the channel information together with settings, which are closely related with the channel. Data word 2 holds setup information, which is adjusted during production. 5.1 MSB Data Word 1 LSB Add. bit D12 D11 D10 D9 1 GF D8 D7 D6 D5 D4 D3 D2 D1 D0 A0 VCODAC CPCS GF 1 SC MC VCOs 1 MCC GFCS Data Bits D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 RC 5.2 Data Word 2 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 MCCS TEST A0 0 DEMODDAC 18 T2801 4567B-DECT-03/06 T2801 6. Data Word 1 Programs 6.1 PLL Settings Table 6-1. D22 0 0 1 With the Reference Counter Bits D21-D22 RC (Referene Counter) D21 0 1 0 SRC 3 4 6 REF_CLK (MHz) 10.638 13.824 20.736 Table 6-2. With the Main Counter Bits D14-D15 MC (Main Counter) D15 0 0 1 1 D14 0 1 0 1 SRC 32 33 34 35 Table 6-3. D20 0 0 0 ... 1 1 1 With the Swallow Counter Bits D16-D20 SC (Swallow Counter) D19 0 0 0 1 1 1 D18 0 0 0 1 1 1 D17 0 0 1 0 1 1 D16 0 1 0 1 0 1 SSC 0 1 2 ... 29 30 31 6.2 VCO Select (RX/TX VCO) Table 6-4. D13 0 1 Note: Used to switch between RX/TX VCO With bit D13 VCOS (VCO Select) RX-VCO TX-VCO 19 4567B-DECT-03/06 6.3 Gaussian Filter On/Off Table 6-5. D10 0 1 Note: GF is used only in TX mode With bit D10 GF (Gaussian Filter) OFF ON 6.4 Modulation Compensation Circuit On/Off Table 6-6. D9 0 1 Note: MCC is used only in TX mode With bit D9 MCC (Modulation Compensation Circuit) OFF ON 6.5 GFCS Adjustment Table 6-7. D8 0 0 0 0 1 1 1 1 Note: With bit D6 - D8 GFCS(Gaussian Filter Settings) D7 0 0 1 1 0 0 1 1 D6 0 1 0 1 0 1 0 1 GFCS (%) 60 70 80 90 100 110 120 130 Only in TXmode effective for setting the frequency deviation of the modulation 20 T2801 4567B-DECT-03/06 T2801 6.6 VCO_DAC Adjustment Table 6-8. D5 0 0 0 0 1 1 1 1 Note: With bit D3 - D5 Pretune DAYC Voltage D4 0 0 1 1 0 0 1 1 D3 0 1 0 1 0 1 0 1 fVCO/% -5 ... ... ... ... ... ... 5 Used to pretune the VCO frequency in case of production tolerances of the device. Tuning voltage in locked condition should be around 1.8V at room temperature. This gives margin for ambient temperature changes 6.7 CPCS Adjustment Table 6-9. D2 0 0 0 0 1 1 1 1 Note: With bit D0 - D2 CPCS (Charge-pump Current Settings) D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 CPCS -4 -3 -2 -1 0 1 2 3 Used to adjust the charge pump current. This can be used to compensate the change of the tuning sensitivity over frequency and device tolerances 21 4567B-DECT-03/06 7. Data Word 2 Programs 7.1 DEMODDAC Adjustment Table 7-1. E10 0 0 0 1 1 1 Note: E9 0 0 0 1 1 1 With bits E6 - E10 Demod DAC Voltage E8 0 0 0 1 1 1 E7 0 0 1 0 1 1 E6 0 1 0 1 0 1 fIFcenter (%) -5 ... ... ... ... ... 5 Only in RX mode effective. Used to tune the demodulator center frequency and allows to compensate tolerances of extenal components and the T2801 7.2 MCCS Adjustment Table 7-2. With bits E3 - E5 MCCS (Modulation Compensation Settings) E5 0 0 0 0 1 1 1 1 Note: E4 0 0 1 1 0 0 1 1 E3 0 1 0 1 0 1 0 1 MCCS (%) 60 70 80 90 100 110 120 130 Only in TX mode effective. Adjusts the modulation compensation circuit for closed loop modulation. This adjustment is done with a test sequence of a long stream of ,1' - ,0'. The correct setting is achieved, if the modulation is not affected by the PLL 22 T2801 4567B-DECT-03/06 T2801 7.3 TEST Mode Settings Table 7-3. D11 1 0 1 X 1 0 1 X Note: With bit E0 - E2 and D11 E2 0 0 0 0 1 1 1 1 E1 0 0 1 1 0 0 1 1 E0 0 1 0 1 0 1 0 1 Signal at Lock Detect Output Lock detect RC out/2 PC out/2 MCCTEST: RC out diviced by 512 Lock detect RC out/2 PC out/2 GFTEST: RC out CP Mode Active Active Active Active High imp. High imp. High imp. High imp. In normal operation Lock detect output is used. All other settings are for test only Figure 7-1. DATA 3-wire Bus Protocol Timing Diagram CLOCK ENABLE TPER TL TS TC TH TEC TT Table 7-4. Description Clock period 3-wire Bus Protocol Symbol TPER TS TH TC TL TEC TT Minimum Value 125 60 60 60 200 0 250 Unit ns ns ns ns ns ns ns Set time data to clock Hold time data to clock Clock pulse width Set time enable to clock Hold time enable to data Time between two protocols Figure 7-2. TX DATA Timing RefCLK TX_DATA TS TH Table 7-5. Parameters TX DATA Timing Values Symbol TS TH Value 10 ns 10 ns Remarks TS and TH must be considered for both (falling and rising) edges of RefCLK when using REF_CLK = 10.368 MHz. Set-up time TX DATA Hold time TX DATA 23 4567B-DECT-03/06 8. Absolute Maximum Ratings Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages refer to GND Parameters Supply voltage regulator, Pin 10 Supply voltage, pins 7, 12, 14, 33 and 42 Logic input voltage, pins 1, 2, 3, 38, 39, 44, 45, 46, 47 and 48 Junction temperature Storage temperature Symbol VS_REG VS VIN Tjmax TStg -40 Min. 3.2 3.0 -0.3 Max. 4.7 4.7 VS 150 +150 Unit V V V C C 9. Thermal Resistance Parameters Junction ambient Symbol RthJA Value TBD Unit K/W 10. Operating Range Parameters Supply voltage regulator, Pins 10 Supply voltage, pins 7, 12, 14, 33 and 42 Ambient temperature Symbol VS_REG VS Tamb Min. 3.2 3.0 -25 Typ. 3.6 3.0 Max. 4.6 4.6 +85 Unit V V C 24 T2801 4567B-DECT-03/06 T2801 11. Electrical Characteristics Test conditions (unless otherwise specified): VS_REG = 3.2V, Tamb = 25C Parameters IR Mixer, Pins 29, 30, 40 and 41 Input impedance Input matching Image rejection ratio DSB noise figure Conversion gain Input interception point IF Amplifier, Pins 26, 27, 34 and 35 Input impedance Lower cut-off frequency Upper cut-off frequency Power gain Bandwidth of external tank circuit Noise figure RSSI, Pins 25, 34 and 35 RSSI sensitivity RSSI compression RSSI dynamic range RSSI resolution RSSI rise time RSSI fall time Quiescent output voltage Maximum output voltage Slope of the RSSI has to be steady Pin = 30 to 100 dBV, pin 25 Pin = 100 to 30 dBV, pin 25 At Pin < 20 dBV at IF_IN1, IF_IN2, pin 25 At Pin = 100 dBV at IF_IN1, IF_IN2, pin 25 At Pin = -75 dBm at IR-mixer input Quality factor of external tank circuit approximately 20, fres = FIF/2, Pin 24 Nominal deviation of signal 288 kHz, Pin 24 Pin 23: C = 68 pF Pin 24 (see bus protocol E6 ... E10) At IF_IN1, IF_IN2 Pins 34 and 35 At IF_IN1, IF_IN2 Pins 34 and 35 Pmin Pmax DR Acc tr tf Iout Iout 20 100 80 2 1 1 0.45 2.25 dBV dBV dB dB s s A A Pins 26 and 27 Pins 34 and 35 Zin fl3dB fu3dB Gp BW3dB NF 200 90 130 85 10 9 400 MHz MHz dB MHz dB Pins 29 and 30 Pins 29 and 30 Pins 40 and 41 Pins 40 and 41 Rload = 200 Pins 40 and 41 Zin VSWRin IRR NFDSB = NFSSB Gconv IIP3 50 < 2:1 20 10 11 -10 dB dB dB dBm Test Conditions/Pins Symbol Min. Typ. Max. Unit FM Demodulator, BB-Filter Pins 19, 20, 23 and 24 Co-channel rejection ratio CCRR 10 dB Sensitivity S 0.5 V/MHz Amplitude of recovered signal Corner frequency Output voltage DC range DEMOD_DAC range A fc VoutDC fIFcenter 1 450 680 Vs - 1 5 mVss kHz V % DAC for FM Demodulator (Internally Connected) 25 4567B-DECT-03/06 11. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2V, Tamb = 25C Parameters VCO RX-VCO frequency range TX-VCO frequency range Tuning gain Frequency control voltage range VCO_DAC range PLL Scaling factor prescaler Scaling factor main counter Scaling factor swallow counter External reference input frequency External reference input voltage Scaling factor reference counter Charge Pump, Pin 13 Output current Output current Current scaling Leakage current Gaussian Transmit Filter (Gaussian Shape B x T = 0.5) Tx data filter clock Frequency deviation Frequency deviation scaling Modulation Compensation Circuit Oversampling Digital sum variation Current scaling factor VCO Switch and TX Driver, Pin 32 Power gain Output impedance Maximum output power Gain compression Output interception point At Pin = -40 dBm Pin 32 Pin 32 At TX_RF_OUT, Pin 32 Pin 32 Gp Zout Pmax P1dB OIP3 0 30 100 3 1 10 dB dBm dBm dBm (see bus protocol E3 ... E5) OVS DSV MCCS 60 6 85 130 % GFFM = GFFM_nom x GFCS (see bus protocol D6 ... D8) 12 taps in filter fTXFCLK GFFM_nom GFCS 60 13.824 350 130 MHz kHz % VCP = VVS_CP / 2, I_CPSW = `1', pin 48 VCP = VVS_CP / 2, I_CPSW = `0', pin 48 ICP = ICP_nom + CPCS x ICP_step (see bus protocol D0 ... D2) ICP_nom ICP_nom ICP_step IL 6.5 1.2 0.2 100 mA mA mA pA AC coupled sinewave, pin 4 AC coupled sinewave, pin 4 SPSC SMC SSC fREF_CLK VREF_CLK SRC 50 3/4/6/8 0 10.368 13.824 20.736 250 32/33 32/33/34/35 31 MHz MHz MHz mVRMS Pin 17 (see bus protocol D3 ... D5) VCOS = `0' Bit D13 VCOS = `1' Bit D13 fvco fvco Gtune Vtune fvco,DAC 0.4 5 1769 1881 40 2.8 1824 1934 MHz MHz MHz/V V % Test Conditions/Pins Symbol Min. Typ. Max. Unit 26 T2801 4567B-DECT-03/06 T2801 11. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2V, Tamb = 25C Parameters Ramp Generator, Pins 36 and 37 Minimum output voltage Maximum output voltage Rise time Fall time According to RAMP_SET input According to RAMP_SET input Cramp = 270 pF at pin 37 Cramp = 270 pF at pin 37 Locked = `1', unlocked = `0' Test modes (see bus protocol E0 ... E2) VOH = 4.6V IOL = 0.5 mA VSREG = 3V, pin 8 VPin10 = VDC + 0.1Vpp fPin10 = 0.1 to 10 kHz CPin8 = 100 nF VSVCO = 3V, pin 15 Vmin Vmax tr tf 0.7 2.2 5 5 V V s s Test Conditions/Pins Symbol Min. Typ. Max. Unit Lock Detect and Test Mode Output Pin 5 Lock detect output, test mode output Leakage current Saturation voltage Output voltage Supply voltage rejection LD IL VSL VREG SVR 2.9 3.0 TBD 5 0.4 3.1 A V V dB Auxiliary Regulator, Pins 8, 9 and 10 VCO Regulator; Pins 14, 15 and 12 Output voltage 3-wire Bus Clock High input level Low input level High input current Low input current Power up PU_REG = `1` PU_RX/TX = `1` PU_PLL = `1` High input level Standby PU_REG = `0` PU_RX/TX = `0` PU_PLL = `0` Low input level Power up PU_REG = `1` PU_RX/TX = `1` PU_PLL = `1` High input current Standby PU_xxxx = `0' Low input current = `1' = `0' = `1' = `0' fClock ViH ViL IiH IiL -5 -5 1.5 0.5 5 5 6.912 MHz V V A A Logic Input Levels (CLOCK, DATA, ENABLE, RX_ON, TX_ON, PU_VCO, TX_DATA, I_CPSW), Pins 1, 2, 3, 38, 39, 44, 47 and 48 VREG_VCO 2.6 2.7 2.8 V Standby Control, Pins 6, 45 and 46 Pin 6 Pin 45 Pin 46 VPU_REG VPU_RX/TX VPU_PLL 2.0 V Pin 6 Pin 45 Pin 46 VPU_REG,OFF VPU_RX/TX,OF F VPU_PLL,OFF 0.7 V VPU = 3V, pin 6 VPU = 5.5V, pin 45 VPU = 3V, pin 46 VPU = 5.5V VPU = 0V, pin 6, VPU = 0.5V, pins 45, 46 IPU_REG IPU_RX/TX IPU_PLL 20 60 100 200 30 80 125 300 40 100 150 400 0.1 1 A A A A A A IPU,OFF 27 4567B-DECT-03/06 11. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2V, Tamb = 25C Parameters Settling Time VS = 0 active operation Settling Time Standby active operation Settling Time Aactive operation standby Total supply current Total supply current Total supply current Total supply current Standby current Supply current CP Test Conditions/Pins Switched from VS = 0 to VS = 3V Switched from PU = `0' to PU = `1' Switched from PU = `1' to standby RX RSSI only TX TX (MCC, GF active) PU_RX/TX = GND VVS_CP = 3V, PLL in lock condition, pin 13 Symbol tsoa tssa tsas IS IS IS IS IS ICP 1 Min. Typ. < 10 < 10 <2 85 82 54 58 10 Max. Unit s s s mA mA mA mA A A Power Supply Pins 7, 10, 12, 14, 33 and 42 28 T2801 4567B-DECT-03/06 T2801 12. T2801 Aplication Circuit RAMP_OUT 33 pF 180 nH 100 nH SAW Filter TFS 112B 33 pF 18 pF 15 pF 68 pF G N D 3 31 G N D 2 28 R F _ IN 2 3 0 R AM P_O U T 36 IF _ IN 2 3 5 T X_O U T 32 R F _ IN 1 2 9 IF _ IN 1 3 4 V S _ IF 3 3 IF _ T A N K 2 2 7 IF _ T A N K 1 2 6 R SSI 25 TX_OUT RF_IN RSSI 270 nH 15 pF 560 pF RX_ON TX_ON 37 RAMP_SET 38 RX_ON 39 TX_ON 40 MIXER_OUT1 41 MIXER_OUT2 42 VS_MIXER PU_VCO PU_RX/TX PU_PLL TX_DATA I_CPSW 43 GND_PLL 44 PU_VCO 45 PU_RX/TX 46 PU_PLL BB_OUT 24 BB_CF 23 REG_DEC 22 DAC_DEC 21 DEMOD_TANK2 20 DEMOD_TANK1 19 GND1 18 VTUNE 17 GND_VCO 16 VREG_VCO 15 4 R EF _C LO C K 9 R EG _C TR L 68 pF 2.2 nF 100 pF BB_OUT T2801 tbd tbd 22 nF 180 W 150 nF 11 G N D _C P 47 TX_DATA 3 EN ABLE 1 C LO C K VS_VCO 14 10 VS_R EG 12 VS_C P 6 PU _R EG 7 VS_PLL 48 I_CPSW CP 13 8 VR EG 2 D ATA 5 LD 56 pF 470 nF CLOCK DATA ENABLE REF_CLK LD PU_REG 4.7 nF VCC 220 pF BC808 or similar tantal tantal 29 4567B-DECT-03/06 13. Ordering Information Extended Type Number T2801-PLQ Package QFN48 Remarks Taped and reeled 14. Package Information Package: QFN 48 - 7 x 7 Exposed pad 5.1 x 5.1 (acc. JEDEC OUTLINE No. MO-220) Dimensions in mm 7 0.85+0.15 0.42x45 48 1 36 0.65+0.15 5.5 5.10.15 37 48 1 0.5 0.23-0.05 +0.07 12 +0.04 6.75 10:1 25 24 13 12 0.01-0.01 technical drawings according to DIN specifications 0.4-0.10 Drawing-No.: 6.543-5068.01-4 Issue: 3; 24.01.03 +0.05 30 T2801 4567B-DECT-03/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) Atmel Corporation 2006. All rights reserved. Atmel (R), logo and combinations thereof, Everywhere You Are (R) and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Printed on recycled paper. 4567B-DECT-03/06 |
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